1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a system in package (SIP) having a plurality of semiconductor chips stacked one on another arranged within a package. More particularly, the present invention relates to a configuration of a signal output portion formed on a semiconductor chip within the SIP.
2. Description of the Background Art
A system LSI having a logic performing prescribed processing and a memory storing data necessary for the logic integrated in a semiconductor chip has been employed for the purposes of downsizing, speeding up and reducing power consumption of a data/signal processing system. In the system LSI, the logic and the memory are interconnected by means of on-chip interconnection lines. Due to small load on a signal line, high-speed signal transfer is allowed. As there is no pin terminal between the logic and the memory, they can be interconnected under a pitch condition of an internal interconnection, without restriction by the pitch of pin terminal. This allows an increase in number of data bits, so that high-speed data transfer is achieved.
In this system LSI, a logic, a memory, an analog circuit and others are formed on the common semiconductor chip. Therefore, they should be fabricated in the same manufacturing steps to the greatest possible extent. In the logic, a MOS transistor (insulated gate type field effect transistor) as its component can be miniaturized according to a scaling rule, and the power supply voltage can be decreased.
In a dynamic random access memory (DRAM), a capacitor of a memory cell is used for storage of data. Usually, a capacitor having a stacked structure with a storage node and a cell plate electrode formed on a surface of a semiconductor substrate is employed for the memory cell capacitor. Since this memory cell capacitor is formed on the surface of the semiconductor substrate, a step occurs between the logic and the DRAM. Some measures are taken to reduce such a step; for example, the capacitor having the stacked structure is reduced in height, and a capacitance value of the memory cell capacitor is decreased.
Compared to the logic, the DRAM cell requires a relatively high voltage to store a sufficient amount of charges in the memory cell capacitor. Thus, a gate insulating film of an accessing transistor of the DRAM cell is made thicker than the gate insulating film of the MOS transistor of the logic. In order to prevent various thermal processing steps in manufacture of the DRAM cell from adversely affecting the MOS transistor of the logic, a so-called xe2x80x9cthermal budgetxe2x80x9d in the thermal processing steps is made small, and the time for the heat treatment is shortened compared to the case of manufacturing a DRAM alone.
Thus, in such a system LSI, when a logic and a DRAM are integrated on the same semiconductor chip, performance of the DRAM is sacrificed to some extent.
Similarly, in an analog circuit, a non-volatile semiconductor memory device and others, their power supply voltages should be made higher than that of the logic, for the purposes of accurate processing and transmission of analog signals, data programming/erasing and others.
In a semiconductor chip, miniaturization of the analog circuit and the memory such as a DRAM cannot be advanced to the same degree as miniaturization of the logic circuit, impeding reduction in chip size of the system LSI. In the system LSI, the presence of a circuit portion in which elements cannot be miniaturized according to a scaling rule hinders reduction of the chip size, and downsizing of the system.
Further, in a high-frequency circuit and an ultra high speed interface circuit for high-speed operation, elements difficult to mount on a semiconductor chip such as an inductance, a capacitance, and a filter are indispensable. Thus, in such an ultra high speed operating environment, it is extremely difficult to mount all the functions necessary for a system on the same semiconductor chip.
In view of the foregoing problems of the system LSI, a system in package (SIP) has been utilized, in which respective functions constituting a system are formed in separate semiconductor chips, and the chips are mounted and packaged. In this SIP, each function is formed in an individual semiconductor chip. Thus, a circuit block implementing a function can be optimally designed for each function. A hybrid-oriented process is unnecessary, and therefore, the manufacturing steps can also be optimized.
Since each function is formed individually, it is possible to select semiconductor chips of optimal functions for a given purpose, for assembling the chips to form a system. A system meeting an intended use can be manufactured in a short period of time. In addition, formation of the respective functions separately from each other makes it possible to optimize each function in a system.
FIG. 56 schematically shows a cross sectional structure of a three dimensional SIP. Referring to FIG. 56, semiconductor chips CH1 and CH2 are stacked one on another and assembled in a package PK. Semiconductor circuits implementing prescribed functions are formed in respective semiconductor chips CH1 and CH2. Pads PD1 and PD2 are formed on the peripheries of semiconductor chips CH1 and CH2, respectively. FIG. 56 shows, by way of example, a state where pad PD2 of semiconductor chip CH2 is connected to pad PD1 of semiconductor chip CH1, and the pad PD1 is also connected to an external terminal through bonding wire. Such utilization of pad PD1 as an intermediate pad lowers the height of wiring. The wire connected to pad PD1 is connected to a lead (not shown).
A bump ball BP connected to a lead is formed on the backside of package PK. Bump ball BP is used as an externally connecting terminal when mounted on a board.
FIG. 57 schematically shows planar arrangement of the semiconductor chips in the SIP shown in FIG. 56. Referring to FIG. 57, pads PD1 are arranged on the periphery of semiconductor chip CH1. A prescribed one of these pads PD1 is connected to the connecting terminal (or the bump ball) via bonding wire WIR1. Semiconductor chip CH2 has pads PD2 arranged on both longer sides thereof. A prescribed one of the pads PD2 is connected via bonding wire WIR2 to a pad of semiconductor chip CH1, and another prescribed one of pads PD2 is connected via bonding wire WIR3 to an external terminal.
In the configuration of the SIP shown in FIGS. 56 and 57 signals/data can be transmitted between semiconductor chips CH1 and CH2 via the bonding wire. Semiconductor chips CH1 and CH2 also can communicate signals/data with an external device.
Semiconductor chips CH1 and CH2 are interconnected by wire WIR2 within the package, and signals/data are transferred between the chips. The interconnection length between the chips can be shortened, and signals/data can be transferred at high speed.
FIG. 58 schematically shows a cross sectional structure of another SIP. In the SIP shown in FIG. 58, a semiconductor chip CH4 is mounted facing down on a semiconductor chip CH3. Semiconductor chip CH4 is connected to semiconductor chip CH3 via a micro bump MBP formed in a pad region.
Semiconductor chip CH3 has a pad PD3 arranged in its peripheral region. Bonding wire WIR4 is formed to pad PD3, through which semiconductor chip CH3 is electrically connected to an external terminal (or a bump ball) via a lead.
In this package PKA, a bump ball BP is formed on the backside of package PKA for connection to an external device.
In the SIP shown in FIG. 58, semiconductor chip CH4 is connected to an internal node of semiconductor chip CH3 via micro bump MBP. Micro bump MBP has pad capacitance substantially the same as that of an on-chip interconnection line, and high-speed signal/data transfer between semiconductor chips CH3 and CH4 can be achieved. In particular, since semiconductor chip CH4 is mounted facing down on semiconductor chip CH3 and the chips are interconnected by micro bumps MBP, interconnection distance between chips CH3 and CH4 can be shortened, and interconnection lengths therebetween can be equalized. High-speed signal/data transfer is thus achieved.
In the case where semiconductor chips CH3 and CH4 are directly interconnected using micro bumps MBP, rearrangement of pad regions of semiconductor chips CH3 and CH4 is carried out generally at the designing stage. When existing semiconductor chips are utilized, an intermediate layer called an interposer is placed between semiconductor chips CH3 and CH4, and re-wiring for changing interconnection paths is performed in the interposer.
FIG. 59 schematically shows planar chip layout of the SIP shown in FIG. 58. Referring to FIG. 59, semiconductor chip CH4 is mounted facing down on semiconductor chip CH3. A pad PD4 formed on semiconductor chip CH4 is directly connected to a pad region formed in semiconductor chip CH3 via micro bump MBP shown in FIG. 58. A pad PD3 formed on the periphery of semiconductor chip CH3 is electrically connected to an external terminal (or a bump ball) via bonding wire WIR4 and a lead (not shown).
Semiconductor chips CH3 and CH4 are interconnected via the micro bumps. Thus, interconnection for the chips CH3 and CH4 can be made uniform in height and minimal in length, allowing high-speed signal/data transfer. Since the chips are interconnected using the micro bumps, wiring for inter-chip connection is unnecessary. The wires are formed solely for external connection.
As shown in FIG. 59, semiconductor chip CH4 is electrically connected to semiconductor chip CH3 via pad PD4. Pad PD3 arranged on the periphery of semiconductor chip CH3 is used for transferring signals/data to and from an external device. This semiconductor chip CH4 does not perform direct signal/data transfer with the external device.
FIG. 60 schematically shows a configuration of a system implemented by the system in package shown in FIGS. 58 and 59. The system shown in FIG. 60 includes a system logic LSI LG1 and a memory LSI ML. System logic LSI LG1 and memory LSI ML are interconnected via an internal interconnection line IL, through which control signals and data are transferred.
System logic LSI LG1 transfers control signals and data to/from an external device via an external interconnection line OL. Memory LSI ML is only permitted to transfer the control signals and the data to/from system logic LSI LG1 via internal interconnection line IL. The system LSI SYS1 shown in FIG. 60 is a memory and logic merged system, which conventionally has wide applications as a representative of the system LSI.
In the system SYS1 shown in FIG. 60, data are transferred between system logic LSI LG1 and memory LSI ML in separate I/O data buses. Alternatively, a common I/O data bus may be used for bidirectional data transfer between the system logic LSI and the memory LSI.
FIG. 61 functionally shows another configuration of the SIP shown in FIGS. 58 and 59. In the system SYS2 shown in FIG. 61, a system logic LSI LG2 and an analog LSI AL are interconnected via an internal interconnection line INL. System logic LSI LG2 communicates control signals and data with an external device via an external interconnection line OUL.
Analog LSI AL includes a digital/analog converter and an analog/digital converter, and processes analog signals. In this analog LSI AL, processing operations of the analog signals are carried out. For example, it performs an operation of a sigmoid function on a signal indicating a firing condition of neurons in a neural network.
This analog LSI AL may have the SIP configuration as shown in FIGS. 56 and 57, in which case, analog LSI AL and an external device send/receive signals in between. For example, analog LSI AL converts an externally supplied analog image signal to a digital signal and transfers the digital signal to system logic LSI LG2. In this case as well, signal/data transfer between the system logic LSI and the analog LSI is carried out via internal interconnection line INL.
In such an SIP, a circuit implementing a predetermined function is formed on an individual semiconductor chip. Thus, an interface circuit (signal/data input/output circuit) is optimally set for each semiconductor chip.
FIG. 62 shows a signal output portion of a semiconductor chip CHA. Referring to FIG. 62, a pad PDa arranged on semiconductor chip CHA is driven by an output buffer OBF. Upon packaging, pad PDa is connected to another semiconductor chip via an internal interconnection ILa which may be a wire or a micro bump. Internal interconnection ILa has a parasitic capacitance Ca comprised of interconnection capacitance and pad capacitance.
Output buffer OBF has its driving capability and output impedance optimally set to quickly drive the output load including this parasitic capacitance Ca. As described above, internal interconnection ILa is formed of, e.g., a micro bump, whose parasitic capacitance Ca and parasitic resistance are sufficiently small. Thus, the output driving capability of output buffer OBF is also made small. Output buffer OBF with large output driving capability would cause ringing. Impedance mismatching between output buffer OBF and internal interconnection ILa would cause a reflected wave.
For the SIP, semiconductor chips can be tested at a wafer level to detect known good dies (KGD), and only good chips (KGD) can be utilized. Thus, the yield is improved compared to the case of a merged device in which a plurality of functional blocks are formed on the same semiconductor chip at the same time.
When testing a semiconductor chip at a wafer level, as shown in FIG. 63, a test probe TPR is brought into contact with pad PDa of semiconductor chip CHA. An external tester sends and receives various signals/data via test probe TPR, to determine pass/fail of a semiconductor circuit device formed in the semiconductor chip CHA.
In the case when test probe TPR is brought into contact with pad PDa as shown in FIG. 63, load Cp of test probe TPR is extremely large compared to parasitic capacitance Ca of internal interconnection ILa shown in FIG. 62. This is for the following reasons: test probe TPR has an interconnection width of an external interconnection as test probe TPR is connected to the external tester; an interconnection length of a signal line connected between test probe TPR and the external tester is also large; and input capacitance of an input circuit of the external tester is substantially the same as that of an input circuit of an external device after assembly into system.
It is now assumed that output buffer OBF optimally designed to drive the load (parasitic capacitance Ca) connected to internal interconnection ILa is used to send a signal to the external tester via test probe TPR having such large load. In this case, output buffer OBF having the small driving capability cannot drive test probe TPR at high speed, so that an accurate signal waveform cannot be transmitted to the tester. In addition, output buffer OBF cannot transfer signals via test probe TPR at high speed. Accordingly, there arises a problem that semiconductor chip CHA for use in an SIP cannot be tested at a wafer level accurately.
An object of the present invention is to provide a semiconductor device suitable for an SIP allowing accurate testing at a wafer level.
Another object of the present invention is to provide a semiconductor device suitable for an SIP allowing accurate testing at a wafer level without adversely affecting its operation when mounted in the SIP.
The semiconductor device according to a first aspect of the present invention includes a first output buffer coupled to an output pad and driving the output pad with first driving capability in accordance with an internal signal when enabled, and a second output buffer coupled to the output pad and driving the output pad with second driving capability greater than the first driving capability in accordance with the internal signal when enabled. The first output buffer is enabled in a normal operation mode, and set to an output high impedance state in a test operation mode. The second output buffer is enabled in the test operation mode, and set to an output high impedance state in the normal operation mode.
The semiconductor device according to a second aspect of the present invention includes a first output buffer coupled to an output pad and enabled in a normal operation mode and set to an output high impedance state in a test operation mode, and driving the output pad with first driving capability in accordance with an internal signal when enabled, and a second output buffer coupled to the output pad and enabled in the test operation mode and set to an output high impedance state in the normal operation mode, and driving the output pad with second driving capability greater than the first driving capability in accordance with the internal signal when enabled. The second output buffer includes first and second insulated gate type field effect transistors coupled to the output pad and complementarily rendered conductive in accordance with the internal signal and driving the output pad when conductive.
The semiconductor device according to the second aspect of the present invention further includes a back gate voltage generating circuit which is selectively activated in accordance with an operation mode designating signal and generates, when activated, a bias voltage to be applied to a back gate of at least one of the first and second insulated gate type field effect transistors. The back gate voltage generating circuit includes a clock generating circuit for generating a pumping clock signal when activated, a pumping circuit for generating a bias voltage through a charge pumping operation of a capacitor in accordance with the pumping clock signal, and a detecting circuit for detecting an output voltage level of the pumping circuit and selectively activating a pumping clock generating operation of the clock generating circuit in accordance with the detection result.
The semiconductor device according to a third aspect of the present invention includes an output buffer having an output transistor coupled to an output pad and driving the output pad in accordance with an internal signal, and a back gate voltage setting circuit for changing a back gate voltage of the output transistor in accordance with an operation mode. The back gate voltage setting circuit sets the voltage level of the back gate voltage such that driving capability of the output transistor in a test mode of operation becomes greater than in a normal operation mode.
According to the first and second aspects of the present invention, the first output buffer operating in the normal operation mode and the second output buffer with large driving capability operating in the test operation mode are provided for the output pad. Even if a test probe having large load is brought into contact with the output pad in the test operation mode, the second output buffer with the large driving capability can generate a signal of accurate signal waveform in accordance with the internal signal and drive the test probe at high speed. This ensures accurate testing of the semiconductor device.
In the normal operation mode, the output pad is coupled to an input node of another semiconductor chip. In this normal operation mode, the first output buffer having the driving capability corresponding to the load of the output pad in the normal operation is enabled to drive the output pad in accordance with the internal signal. Therefore, in the normal operation mode, the output pad can be driven in accordance with the internal signal with the optimal driving capability corresponding to the load of the output pad, and signals/data can be transferred between chips at high speed. In the normal operation mode, the second output buffer is set to the output high impedance state, so that it does not adversely affect the inter-chip signal transfer in the normal operation.
The transistor of the output buffer for use in testing can be downsized by adjusting the back gate voltage thereof, and the driving capability of this testing output transistor can readily be increased upon testing. In a normal operation mode, the load on the output pad is decreased with such a testing output transistor of a small size, and the output pad is driven at high speed in accordance with the internal signal in the normal operation.
The back gate voltage of a desired voltage level can be internally generated with accuracy by generating the back gate bias voltage using a charge pumping circuit and by detecting the level of the back gate bias voltage and controlling the pumping operation in accordance with the result of detection. Accordingly, the testing output buffer having necessary operating characteristics can readily be achieved.
According to the third aspect of the present invention, the output buffer is commonly provided for the test mode of operation and the normal operation, and its back gate voltage is adjusted in accordance with the operation mode. Thus, it is possible to decrease output load and output load driving capability in the normal operation mode. In the test operation mode, test results can be transferred to a tester with an increased driving capability.
In addition, it is unnecessary to provide an output buffer dedicated to testing. This reduces the area occupied by the output circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.